Typical examples of random access semiconductor memory devices are SRAM and DRAM. SRAM is faster in read and write operations than DRAM. SRAM is free of any refresh operations which are needed by DRAM. SRAM is thus more convenient in operations and smaller in data holding current in stand-by state. In contrast, each memory cell of SRAM needs six transistors. SRAM is larger in chip size and more expensive than DRAM.
Each memory cell of DRAM comprises a single capacitor and a single transistor. DRAM has a larger memory capacity at a smaller chip size than SRAM. DRAM is lower in cost than SRAM, provided that both have the same memory capacity. It is, however, necessary for DRAM that column and row addresses are given to DRAM separately from each other, provided that DRAM takes the column address at a timing defined by RAS (a row address strobe signal), and also takes the row address at another timing defined by CAS (a column address strobe signal). DRAM, therefore, needs RAS and CAS as well as needs a control circuit for cyclical refresh operations to memory cells. DRAM is more complicated in timing control and larger in comsumption of current than SRAM.
The majority of the semiconductor memory devices used in portable electronic devices typically portable telephones is SRAM for the following reasons. SRAM is smaller in stand-by current and lower in comsumption of power, for which reason SRAM is suitable for a portable telephone device which needs improvements in a long continuous communication time and in a long continuous stand-by time. Notwithstanding, the conventional portable telephone device had a simple function and does not need a semiconductor memory device with a large capacity. SRAM is easy in the timing control.
Meanwhile, the latest portable telephone device has an additional function of transmission and receipt of e-mails and a still additional function of both making an access to a WEB server on the Internet and subsequently displaying simplified contents of home pages. It is presumable that, similarly to the present personal computers, a future portable telephone device is capable of making a free access to home pages on the Internet. In order to realize such the above-described additional functions, a graphic display is essential for serving a variety of multimedia informations to user, and also a semiconductor memory device with a large capacity is needed for temporary storing, in the portable telephone device, a large amount of data received through public networks.
On the other hand, the portable telephone device needs a small size, a light weight and a low power consumption, for which reason the semiconductor memory device has an increased capacity, while it is desired to avoid increases in size, weight and power comsumption of the semiconductor memory device. As the semiconductor memory device integrated in the portable telephone device, DRAM is preferable in view of a large capacity, while SRAM is preferable in another view of operability and power comsumption. Such a semiconductor memory device as having both advantages of SRAM and DRAM seems optimum for the portable electronic devices.
As such the above-described semiconductor memory device, a “pseudo-SRAM” has been proposed, which uses the same memory cells as DRAM and have the same specifications and the same operations as SRAM in view of user side. The pseudo-SRAM is disclosed in Japanese laid-open patent publications Nos. 61-5495, 62-188096, 63-206994, 4-243087 and 6-36557.
Since the pseudo-SRAM has the same memory cell structure as DRAM, it is necessary for the pseudo-SRAM to perform cyclically refresh operations for holding data stored in memory cells thereof. The pseudo-SRAM is free of such a stand-by mode as of the conventional SRAM, even the pseudo-SRAM is similar in operations to the SRAM. It is preferable that the pseudo-SRAM has such a low power consumption mode as the general-purpose SRAM in view of operability as long as the pseudo-SRAM is operated in the same specification as the conventional SRAM.
The present inventions proposed, in view of the above-perspective, a semiconductor memory device which has a unique low power consumption mode different from the existent semiconductor memory device, and which has a stand-by mode equivalent to the stand-by mode of the general-purpose SRAM, with reference to the semiconductor device using the pseudo-SRAM, wherein the semiconductor memory device is disclosed in Japanese patent application No. 2000-363664 (Japanese laid-open patent publication No. 2002-74944 and International Publication No. WO01/41149A1. In accordance with this conventional invention, two different operation modes are set. The first operation mode is a stand-by mode as the same power supply mode as in the normal DRAM for supplying a power to circuits necessary for refresh of memory cells in order to ensure data hold of the memory cells. The second operation mode is a deep stand-by mode which discontinues any power supply to the circuits necessary for the refresh of the memory cells, thereby not ensuring the data hold of the memory cells.
In this deep stand-by mode, it is impossible to hold the data of the memory cells, but any refresh operation is unnecessary. This reduces the consumption of current in the deep stand-by mode as compared to the stand-by mode. This deep stand-by mode is available as long as all memory cells of the memory cell array become allowed for write operations during a transition from the stand-by state into the active state. This deep stand-by mode is suitable for using the semiconductor memory device as a buffer.
FIG. 1 is a block diagram illustrative of one example of the configuration of the essential part of the conventional pseudo SRAM. In FIG. 1, a voltage level control circuit 1 generates an internal voltage level control signal “A” based on first and second reference voltages Vref1 and Vref2. This internal voltage level control signal “A” is a signal for controlling a level of a boost voltage Vbt to be applied to word lines of a memory cell array 2. The internal voltage level control signal “A” is outputted from the voltage level control circuit 1 and then inputted into a ring oscillator 3. The ring oscillator 3 is activated and oscillated by “H” (high level) of the internal voltage level control signal “A” from the voltage level control circuit 1, whereby the ring oscillator 3 outputs an oscillation output “B”. The oscillation output “B” outputted from the ring oscillator 3 is then inputted into a boost circuit 4.
The boost circuit 4 comprises a charge pump circuit for generating the boost voltage Vbt as an internal voltage. The boost circuit 4 boosts step-by-step a power voltage VDD by utilizing the oscillation output “B” outputted from the ring oscillator 3 for generating the boost voltage Vbt. This boost voltage Vbt is then inputted into a word decoder 5 for driving a word line. The boost voltage Vbt is set at a level which is higher than the power voltage VDD, for example, about VDD+1.5V to VDD+2V. The word decoder 5 supplies the boost voltage Vbt to a word line selected by an output from a row decoder 6. The memory cell array 2 comprises the same configuration as the memory cell array of DRAM.
A refresh timing generation circuit 7 generates a refresh signal and a refresh address, wherein the refresh signal is to refresh memory cells in the memory cell array 2 at a constant time interval, while the refresh address is to designate an address of a memory cell which should be refreshed. The refresh signal is outputted from the refresh timing generation circuit 7 and then inputted into a row enable generation circuit 8. The refresh address is outputted from the refresh timing generation circuit 7 and then inputted into the row decoder 6. The row enable generation circuit 8 generates a row enable signal LT at a timing when the refresh timing generation circuit 7 generates the refresh signal.
The row enable generating circuit 8 receives inputs of a write enable signal WE, a chip select signal CS and a read/write address Add of the memory cell array 2, and outputs the row enable signal LT every time the read/write address Add is transitioned. The row enable signal LT is inputted into the voltage level control circuit 1 and the row decoder 6.
FIG. 2 is a timing chart illustrative of an operation of the circuit shown in FIG. 1 in a stand-by mode. An operation of generating a boost voltage for refreshing memory cells will hereinafter be described with reference to FIGS. 1 and 2.
If the pseudo-SRAM is placed in the stand-by state, then the refresh signal is outputted from the refresh timing generation circuit 7 at a constant cycle, for example, 16 microseconds, and then the refresh signal is supplied to the row enable generation circuit 8. The row enable generation circuit 8 generates receives an input of the refresh signal and generates a row enable signal LT and then supplies the row enable signal LT to the voltage level control circuit 1. The voltage level control circuit 1 is activated by the row enable signal LT, whereby the voltage level control circuit 1 compares the boost voltage Vbt to the first and second reference voltages Vref1 and Vref2. If the boost voltage Vbt is lower than the first reference voltage Vref1, then the internal voltage level control signal “A” becomes “H” (high level), whereby the ring oscillator 3 starts an oscillation and supplies the oscillation output “B” to the boost circuit 4.
The boost circuit 4 boosts the boost voltage Vbt by using the oscillation output “B”. After the boost voltage Vbt is boosted to reach the same level as the second reference voltage Vref2, then the voltage level control circuit 1 sets the internal voltage level control signal “A” at “L” (low level), whereby the oscillation of the ring oscillator 3 is discontinued, and thus the boosting operation of the boost circuit 4 is discontinued. During this cycle, the refresh operation is executed to the memory cells in the memory cell array 2.
In the stand-by mode, the refresh timing signal is automatically generated at a cycle which ensures holding data, together with placing the voltage level control circuit 1 into the power ON state, in order to hold the word level at not less than the reference voltage Vref1. Except when the refresh timing, the voltage level control circuit 1 is placed into the power OFF, in order to both ensure the data hold and reduce the consumption of current.
The pseudo SRAM is transitioned from the stand-by state into the active state, so that the chip select signal CS is risen and then the read/write address Add is then transitioned, whereby the row enable generation circuit 8 detects this transition and outputs the signal LT for activating the voltage level control circuit 1. Accordingly, in the active state, boosting operation of the boost voltage Vbt is made every time accesses to memory cells are made.
FIG. 3 is a block diagram illustrative of an example of a configuration of a conventional timing cycle generation circuit in the refresh timing generation circuit. The timing cycle generation circuit comprises an OR-gate 11 and a timer circuit 12, wherein the OR-gate 11 receives inputs of both an operation mode selecting signal MODE for switching between a deep stand-by mode and a stand-by mode and a chip select signal CS, and the timer circuit 12 receives an output from the OR-gate 11 and outputs a timer signal TN with a constant cycle for refresh operation when the output signal is “H” (high level). A self-refresh cycle of the memory cells in the stand-by mode is set by this timer signal TN.
FIG. 4 is a timing chart illustrative of an operation of the pseudo-SRAM shown in FIG. 1, which incorporates the timing cycle generation circuit shown in FIG. 3.
As shown in FIG. 4, in the deep stand-by mode, any power supply to the pseudo-SRAM shown in FIG. 1 is completely discontinued. Any power supply to the circuit necessary for refresh is also discontinued. Thus, the boost voltage Vbt of the boost circuit 4 is lowered almost to the ground potential. By switching the deep stand-by mode into the stand-by mode, the power supply to the pseudo-SRAM shown in FIG. 1 is re-started and thus the power supply to the circuit necessary for refresh is also made, whereby the refresh timing generation circuit 7 outputs refresh signals at a constant cycle, and the boost voltage Vbt of the boost circuit 4 is also increased.
The transition to the stand-by state is completed when the boost voltage Vbt is risen up to the first reference voltage Vref1, thereby enabling any active operations such as accesses to the memory. As shown in FIG. 4, however, it takes a time that the boost voltage Vbt lowered down to almost the ground potential in the deep stand-by mode is risen up to the first reference voltage Vref1 in the stand-by state.
Normally, a time of approximately 200 microseconds is set for boosting the voltage as the stand-by time until he pseudo-SRAM is started up and placed into an memory accessible state. During this time, any active operations are inhibited.
In the future, the necessary memory capacity will be further increased. In this case, a load to the boost circuit is also further increased, thereby making longer a time to rise up to the stand-by state. It is estimated that a voltage rising time of 200 micrometers is insufficient for rising up to the stand-by mode.